1. Field of the Invention
The present invention relates generally to an apparatus and method for controlling memory and, more particularly, to an apparatus and method for controlling memory, which are capable of adaptively processing a plurality of commands to access memory in a system-on-chip (SOC) based system.
2. Description of the Related Art
Because of the worldwide smart phone and tablet personal computer (PC) boom, the development of a variety of application processors (APs) has been brought about, and system-on-chips (SOCs) in a variety of fields have come to have a platform structure similar to that of application processors. Such an SOC is characterized in that a plurality of processors or masters is provided therein and shares single memory. In particular, there are many cases in which the performance of systems for processing multimedia data, such as a moving image or music, or for processing a large amount of data at high speed so as to perform recognition and authentication is dependent chiefly on memory access. That is, if memory does not provide sufficient bandwidth, a master, such as a processor or a hardware accelerator, waits for data and experiences a reduction in performance. If only the bandwidth is problematic, the problem may be solved by using high-speed memory or adding dedicated memory, in which case a new problem, such as an increase in cost or the redesign of a system, frequently occurs. Furthermore, the memory access request of a microprocessor for a general instruction is sensitive to a latency and the memory access request of a multimedia hardware accelerator or a microprocessor for multimedia data is sensitive to the sustainable bandwidth, and thus the requirements are different. In order to solve this problem, the system-level control of memory access requests is required. It is very inefficient for a single processor to receive the states of all masters to arbitrate, and to issue control commands. Another approach is for a memory controller to collect memory access commands and to arbitrate so that system performance is optimized. In this case, the transfer of additional information describing the characteristics of each memory access command is necessary.
ARM's Advanced High-performance Bus (AHB) has been widely used as an interface protocol for the transfer of data inside an SOC. The AHB standard allows up to 16 masters, which is effective when the sum of bandwidths required by respective masters is considerably less than the overall bandwidth. If the sum of bandwidths required by respective masters becomes similar to the bandwidth provided by a network, a problem arises even when there are two masters. Although the bandwidth can be considerably increased using an interconnect matrix, it is hardly helpful in the case in which communication is concentrated on shared memory. Another problem of the AHB resides in the fact that it is impossible to perform the operation of arbitrating memory access requests because another master cannot access memory because of stop-and-wait type communication during single memory access communication, and thus a memory controller should sequentially process memory access requests one by one. Although a number of commands equal to the number of interfaces may be processed at one time by increasing the number of slave interfaces, the improvement of performance is not significant in normal cases because of the limitations in which an interconnect matrix should be used and a response should be made via a channel while the corresponding channel is kept open.
In order to solve the problems of the AHB, ARM's AXI supports outstanding addresses and out-of-order completion communication in a multiple-master system and allows register slicing in a network, thereby enabling high-speed operation. Accordingly, since it is possible to handle another memory access request prior to responding to one memory access request, a memory controller can arbitrate access requests. Using this, the effective bandwidth can be increased by reducing the waiting cycles for memory access, and the demand for Quality of Service (QoS) can be met by adjusting the order of priority.
The prior art related to the above technology will be described in greater detail. Korean Patent Application Publication No. 10-2002-0040150 entitled “Synchronous Dynamic Random Access Memory (SDRAM) controller” discloses a controller that adopts SOC technology and contains a memory controller and a variety of types of data or signal processing devices along with SDRAM, thereby improving data transfer efficiency by solving the discrepancy between the data width and the operating frequency between related chips. However, this technology does not take into consideration of the method or sequence of processing multiple commands that attempt to access SDRAM.
Korean Patent Application Publication No. 10-2001-0019127 entitled “External Bus Controller supporting Burst Transfer using MPC860 Processor and SDRAM and Method Thereof” discloses the structure of an external bus controller that provides the maximum performance of a processor, SDRAM and a peripheral component interconnect (PCI) external bus in a variety of processor boards using MPC860 and SDRAM, and an external bus controller that provides the user programmable machine (UPM) of MPC860. This technology is also different from the present invention that is intended to efficiently process multiple commands that attempt to access SDRAM.